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[VHDL-FPGA-Verilog] vhdl0716

Description: ISE7.1，采用VIRTEX-II芯片。实现adc数据采样，平均，通道选择，采样时钟选择，数据格式调整，内含fifo,uart等模块。-ISE7.1, using VIRTEX-II chip. Adc realize data sampling, on average, channel selection, the sampling clock select, adjust data formats, including fifo, uart modules.
Platform: | Size: 8431616 | Author: 杨奋燕 | Hits:

[SCM] rs232

Description: 利用FIFO数据结构,在8051单片机上实现全双工通讯,实现MODBUS通讯协议-Use of FIFO data structure, in 8051 to achieve full-duplex communications, realize MODBUS communication protocol
Platform: | Size: 5120 | Author: 余主恩 | Hits:

[Other Embeded program] uart

Description: ARN7核s3c44b0串口程序源码,包括FIFO,非FIFO多模式的接收发送.-S3C44B0 serial ARN7 nuclear program source code, including FIFO, non-FIFO multi-mode receiver sent.
Platform: | Size: 4096 | Author: 雪莱 | Hits:

[Communication-Mobile] uart

Description: 这个是UART的控制器，已经跑通过，分4个模块，波特率生成、发送、接收和fifo,可供初学者参考-This is the UART controller, has been run through, sub-4 module, baud rate generating, sending, receiving and fifo, for beginners reference
Platform: | Size: 3072 | Author: duan | Hits:

[VHDL-FPGA-Verilog] uart_regs

Description: 可以直接下载到芯片用的带有FIFO的完全UART程序，vhdl语言编写。-Can be directly downloaded to the chip used in the complete UART with FIFO procedures, vhdl language.
Platform: | Size: 388096 | Author: liujingxing | Hits:

[VHDL-FPGA-Verilog] UART

Description: 使用FPGA的FIFO，状态机，乒乓操作等实现了异步UART。-The use of FPGA-FIFO, state machine, ping-pong operation to achieve the asynchronous UART.
Platform: | Size: 1106944 | Author: xiao cao | Hits:

[Com Port] Uart(FIFOSend.TimeoutReceive)

Description: AVR mega16/mega32的UART FIFO发送.超时接收,广泛应用于工业控制.这是原创作品.-AVR mega16/mega32 send the UART FIFO. Overtime receiver is widely used in industrial control. This is the original works.
Platform: | Size: 24576 | Author: 明君 | Hits:

[Other Embeded program] int_uart8051

Description: UART realization for at89c5131 with FIFO and interrupts.
Platform: | Size: 1024 | Author: melg | Hits:

[OS Develop] UART

Description: A badic controller for the UART. It incorporates a -- transmit and receive FIFO (from Max+Plus II s MegaWizard -- plug-in manager). Note that no checking is done to see -- whether the FIFOs are overflowing or not. This strictly -- handles the transmitting and receiving of the data.-A badic controller for the UART. It incorporates a -- transmit and receive FIFO (from Max+Plus II s MegaWizard -- plug-in manager). Note that no checking is done to see -- whether the FIFOs are overflowing or not. This strictly -- handles the transmitting and receiving of the data.
Platform: | Size: 2048 | Author: Viral | Hits:

[DSP program] FIFOSRC

Description: DSP uart窗口通信中的一种通信格式，FIFO模式的一个小程序-dsp serial communication uart communication first in first out-FIFO mode
Platform: | Size: 4096 | Author: luoxin | Hits:

[SCM] FIFO-UART

Description: 基于ARM7-LM3S1138的FIFO方式的UART数据传输代码-ARM7-LM3S1138 based on the FIFO mode of UART data transmission code
Platform: | Size: 44032 | Author: Mr Zhang | Hits:

[VHDL-FPGA-Verilog] pgm

Description: uart vhdl code contains all the neceesary things for a uart of speed 2 mbps and has a fifo of 64 KB
Platform: | Size: 205824 | Author: libin | Hits:

[Other] uart

Description: 此文档为C51单片机串口通讯学习程序（中断+FIFO)-This document is for the C51 microcontroller serial communication learning process (interrupted+ FIFO)
Platform: | Size: 6144 | Author: | Hits:

[Program doc] UART_spec

Description: a UART model with FIFO buffer, design with verilog
Platform: | Size: 145408 | Author: quang | Hits:

[SCM] uart

Description: Also the USART automatically senses the start of transmission of RX line and then inputs the whole byte and when it has the byte it informs you(CPU) to read that data from one of its registers. The USART of AVR is very versatile and can be setup for various different mode as required by your application. In this tutorial I will show you how to configure the USART in a most common configuration and simply send and receive data. Later on I will give you my library of USART that can further ease you work. It will be little complicated (but more useful) as it will have a FIFO buffer and will use interrupt to buffer incoming data so that you are free to anything in your main() code and read the data only when you need. All data is stored into a nice FIFO(first in first out queue) in the RAM by the ISR.
Platform: | Size: 1024 | Author: sstefan | Hits:

[VHDL-FPGA-Verilog] fifouart_latest.tar

Description: vhdl fifo uart core datasheet
Platform: | Size: 176128 | Author: Joe | Hits:

[OS Develop] SC16C752B

Description: The SC16C752B is a dual Universal Asynchronous Receiver/Transmitter (UART) with 64-byte FIFOs, automatic hardware/software flow control, and data rates up to 5 Mbit/s (3.3 V and 5 V). The SC16C752B offers enhanced features. It has a Transmission Control Register (TCR) that stores receiver FIFO threshold levels to start/stop transmission during hardware and software flow control. With the FIFO Rdy register, the software gets the status of TXRDY/RXRDY for all four ports in one access. On-chip status registers provide the user with error indications, operational status, and modem interface control. System interrupts may be tailored to meet user requirements. An internal loopback capability allows on-board diagnostics.
Platform: | Size: 160768 | Author: 刘伟 | Hits:

[VHDL-FPGA-Verilog] Fifoed_avalon_uart_9.3

Description: Altera真正可用的带FIFO的UART组建。-Altera FIFO UART
Platform: | Size: 201728 | Author: we | Hits:

[VHDL-FPGA-Verilog] UART

Description: 基于FPGA的UART设计，包含接收模块，发送模块，FIFO模块-UART FPGA-based design, including the receiver module, sending module, FIFO module
Platform: | Size: 733184 | Author: 钱远盼 | Hits:

[VHDL-FPGA-Verilog] uart

Description: 带有fifo的功能模块，具有发送模块和接收功能模块(The function module with FIFO has transmitting module and receiving function module)
Platform: | Size: 145408 | Author: 陈陈陈啊 | Hits:
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